Semiconductor devices typically include multiple individual components formed on or within a substrate. Such devices often comprise a high density section and a low density section. For example, as illustrated in prior art FIG. 1, a memory device such as a flash memory 10 comprises one or more high density core regions 12 and a low density peripheral portion 14 on a single substrate 16. The high density core regions 12 typically consist of at least one M.times.N array of individually addressable, substantially identical memory cells and the low density peripheral portion 14 typically includes input/output (I/O) circuitry and circuitry for selectively addressing the individual cells (such as decoders for connecting the source, gate and drain of selected cells to predetermined voltages or impedances to effect designated operations of the cell such as programming, reading or erasing).
The memory cells within the core portion 12 are coupled together in a circuit configuration, such as a NAND configuration illustrated in prior art FIG. 2. Each memory cell 20 has a drain 22, a source 24 and a stacked gate 26. Each stacked gate 26 is coupled to a word line (WL1, WL2, . . . , WL8) while the drains 22 and sources 24 are coupled together in series to form a bit line BL through two select gate transistors 27 (SG1 and SG2, respectively). Using peripheral decoder and control circuitry, each memory cell 20 can be addressed for programming, reading or erasing functions.
Prior art FIG. 3 represents a fragmentary cross section diagram of a typical memory cell 20 and a select gate transistor 27 in the core region 12 of prior art FIGS. 1 and 2. The memory cell 20 typically includes the drain 22, the source 24 and a channel 28 in a substrate 30; and the stacked gate structure 26 overlying the channel 28. The stacked gate 26 further includes a thin gate dielectric layer 32 (commonly referred to as the tunnel oxide) formed on the surface of the substrate 30. The stacked gate 26 also includes a polysilicon floating gate 34 which overlies the tunnel oxide 32 and an interpoly dielectric layer 36 overlies the floating gate 34. The interpoly dielectric layer 36 is often a multilayer insulator such as an oxide-nitride-oxide (ONO) layer having two oxide layers 36a and 36b sandwiching a nitride layer 36c. Lastly, a top region 38 overlies the interpoly dielectric layer 36. The top region 38 includes a control gate layer 40 formed of polysilicon, a tungsten silicide layer (WSi.sub.x) 42 which overlies the control gate 40 and a poly cap layer 44 formed predominately of polysilicon.
The control gate 40 provides memory functions for the cell 20 as will be described in greater detail infra while the tungsten silicide layer 42 provides a low resistivity contact as is well known by those skilled in the art. The poly cap layer 44 overlies the tungsten silicide layer 42 and prevents the silicide layer 42 from peeling or cracking. The top regions 38 of the respective cells 20 that are formed in a lateral row (as opposed to a vertical column) share a common word line (WL) associated with the row of cells. The channel 28 of the cell 20 conducts current between the source 24 and the drain 22 in accordance with an electric field developed in the channel 28 by the stacked gate structure 26.
The select gate transistor 27 has a stacked gate structure similar to the memory cell except that the first polysilicon layer 34 and the second polysilicon layer 40 are shorted together to form a single gate type structure. The select gate transistor 27 operates according to traditional MOS transistor principles, wherein SG1 of prior art FIG. 2 ensures the selectivity of the particular bit line, while SG2 prevents the cells from passing current during the programming operation.
According to conventional operation, the flash memory cell 20 operates in the following manner. The cell 20 is programmed by applying a relatively high voltage V.sub.G (e.g., approximately 12 volts) to the control gate 38 and a moderately high voltage V.sub.D (e.g., approximately 9 volts) to the drain 22 in order to produce "hot" (high energy) electrons in the channel 28 near the drain 22. The hot electrons accelerate across the tunnel oxide 32 and into the floating gate 34 and become trapped in the floating gate 34 since the floating gate 34 is surrounded by insulators (the interpoly dielectric 36 and the tunnel oxide 32). As a result of the trapped electrons, the threshold voltage of the cell 20 increases by about 3 to 5 volts. This change in the threshold voltage (and thereby the channel conductance) of the cell 20 created by the trapped electrons is what causes the cell to be programmed.
To read the memory cell 20, a predetermined voltage V.sub.G that is greater than the threshold voltage of an unprogrammed cell, but less than the threshold voltage of a programmed cell, is applied to the control gate 40. If the cell 20 conducts, then the cell 20 has not been programmed (the cell 20 is therefore at a first logic state, e.g., a zero "0"). Likewise, if the cell 20 does not conduct, then the cell 20 has been programmed (the cell 20 is therefore at a second logic state, e.g. a one "1"). Consequently, one can read each cell 20 to determine whether it has been programmed (and therefore identify its logic state).
In order to erase the flash memory cell 20, a relatively high voltage V.sub.S (e.g., approximately 12 volts) is applied to the source 24 and the control gate 40 is held at a ground potential (V.sub.G =0), while the drain 22 is allowed to float. Under these conditions, a strong electric field is developed across the tunnel oxide 32 between the floating gate 34 and the source region 22. The electrons that are trapped in the floating gate 34 flow toward and cluster at the portion of the floating gate 34 overlying the source region 22 and are extracted from the floating gate 34 and into the source region 22 by way of Fowler-Nordheim tunneling through the tunnel oxide 32. Consequently, as the electrons are removed from the floating gate 34, the cell 20 is erased.
During the processing of the core portion 12 having a circuit configuration as illustrated in prior art FIG. 2 and a structure as illustrated in prior art FIG. 3, a problem sometimes occurs involving the formation of poly1 and poly2 contacts, which is illustrated in prior art FIGS. 4a and 4b. A poly1 contact is a contact made to the polysilicon gate 34 of the select gate transistor 27 (wherein poly1 is the first layer of polysilicon) and a poly2 contact is a contact made to the tungsten silicide layer 42 of the top region 38 of the respective memory cells. A conductive layer is then formed over the poly1 and poly2 contact regions to short circuit the first and second layers of polysilicon, as illustrated in FIG. 3.
As illustrated in prior art FIG. 4a, after the select gate transistor 27 is formed, an oxide based interlayer dielectric 46 is formed over the core portion 12. The interlayer dielectric 46 isolates the various word lines and the select gate transistors 27 from overlying conductive layers which are subsequently formed and used to selectively interconnect the various components in the memory device. After the interlayer dielectric 46 is formed, a chemical mechanical polish (CMP) is implemented to polish the interlayer dielectric 46 to a uniform thickness of about 10,000 Angstroms. A photoresist mask (not shown) is then deposited and patterned to define contact openings in the interlayer dielectric 46. A contact etch step is then performed to simultaneously create a contact opening 48 in the interlayer dielectric 46 and the poly cap layer 44 down to the tungsten silicide layer 42 (the poly2 contact) and a contact opening 50 in the interlayer dielectric 46 down to the polysilicon gate 34 (the poly1 contact) for the select gate transistor 27.
The substantial overetch of the poly1 contact opening 50 occurs due to the high oxide-to-polysilicon selectivity of the contact etch. Therefore, although the poly cap layer 44 will be reached first in the poly2 contact opening 48 (before the polysilicon layer 34 is reached in the poly1 contact opening 50), the poly2 contact etch rate will dramatically slow once it reaches the poly cap layer 44 because the poly cap layer 44 is a polysilicon based material and the etch rate with respect to polysilicon is low. Therefore by the time the poly2 contact opening 48 extends through the entire poly cap layer 44 to reach the tungsten silicide layer 42, the poly1 contact opening 50 has reached the polysilicon gate 34 and caused a substantial overetch of the polysilicon gate 34, as illustrated in prior art FIG. 4b.
The substantial overetching of the prior art poly1 contact opening 50 results in potential punch-through problems, wherein the poly1 contact opening 50 extends down through the entire depth of the polysilicon gate 34 and punches through to the substrate 30. Such a punch-through phenomena renders the select gate transistor 27 inoperable, resulting in a functional failure of the memory device.
Alternatively, even if the poly1 contact opening 50 does not extend through the entire polysilicon gate 34, an appreciable portion of polysilicon will be removed which results in an increase in the resultant poly1 contact resistivity. Such an increase in contact resistivity may result in a parametric failure of the memory device or a latent reliability problem as the increased contact resistivity may cause thermal heating which further increases the resistivity of the contact, eventually leading to a device failure.
Consequently, there is a strong need in the art to form memory devices having poly1 and poly2 contacts without a substantial overetching of the poly1 contact.